Active matrix display device

ABSTRACT

In an active matrix display device, gate signals are delayed or distorted as they go to the right due to load of the gate lines and parasitic capacitances of the gate lines and pixels. TP signals for respective blocks of data lines are supplied with time difference such that data signals are applied to the respective blocks of the data lines not in synchronous manner but in a staggered manner. The time difference in the application of the data signals between the data lines is substantially equal to the delay of the gate signals, thereby solving the non-uniform charging of the data signals in the pixels.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to an active matrix display device.

(b) Description of the Related Art

A plurality of display devices such as a liquid crystal display (LCD), afield emission display (FED), a electrolumniesecent (EL) display device,a plasma display panel (PDP) are driven in active matrix type.

The active matrix display devices are driven by applying gate signalsfor turning on and off driving transistors in pixels arranged in amatrix though gate lines. When the gate signals are transmitted from agate driver located at a left side of a display panel, the gate signalsare much delayed and distorted due to load of the gate lines andparasitic capacitances between the gate lines and the pixels as they goto the right.

The signal delay or distortion of the gate signals at the right sidedelays the activation of the driving transistors of the pixels at theright side compared with the driving transistors of the pixels at theleft side. Consequently, the charging time of data signals for therighter pixels become shorter such that the charging of the data signalsfor the pixels at the left and right sides are not uniform since thedata signals for all the pixels are simultaneously applied to datalines. In addition, the delayed gate signals may make the drivingtransistors of the light pixels still activated when the data signalsfor the next row are applied.

Particularly in an LCD subject to an inversion driving, a shadinggenerated by the inverted data voltages for the next row may causesevere horizontal stripes. The width of gate masking may be enlarged forsuch a shading margin.

SUMMARY OF THE INVENTION

A motivation of the present invention is to solve the non-uniformcharging of the data voltages due to the delay of the gate signals.

In order to solve the motivation, the present invention applies datasignals to data lines in a staggered manner.

A display panel according to a first aspect of the present inventionincludes a plurality of data lines extending parallel to each other in acolumn direction and a plurality of gate lines extending parallel toeach other in a row direction. A plurality of pixels receiving gatesignals and data signals respectively from the gate lines and the datalines to display images, each pixel including a switching elementtransmitting the data signals in response to the gate signals arearranged in a matrix. Each pixel includes a switching elementtransmitting the data signals in response to the gate signals. A gatedriver supplies the gate signals to the gate lines, and a data driversupplies the data signals to the data lines in synchronization with aplurality of first control signals. The data lines are grouped into aplurality of blocks, each block including at least one of the data linesand the first control signals correspond to the respective blocks andhave different tiring.

The display device according to the first aspect of the presentinvention may further include a signal controller outputting a timingsignal for driving the display panel and a second control signal, and acontrol signal shifting unit receiving the second control signal andshifting the second control signal in sequence to generating the firstcontrol signals.

Preferably, the control signal shifting unit includes a plurality ofshifters for sequentially shifting the second control signal to betransmitted to adjacent shifters and the first control signals includesthe second control signal and outputs of the shifters.

The display device according to the first aspect of the presentinvention may further include a signal controller outputting a timingsignal for driving the display panel and a second control signal.

A display device according to a second aspect of the present inventionincludes a signal controller outputting a gate control signal forcontrolling the gate signals and a second control signal for controllingthe data signals, respectively. A gate driver supplies the gate signalsto the gate lines in synchronization with the gate control signal fromthe signal controller, and a control signal shifting unit shifts thesecond control signal in sequence to generating a plurality of firstcontrol signals having timing differences. The data lines are groupedinto a plurality of blocks corresponding to the first control signalsand a data driver supplies the data signals to the blocks insynchronization with the first control signals from the control signalshifting unit.

The display device may further include a control signal shifting unitincluding a plurality of shifters sequentially shifting the secondcontrol signal to be transmitted adjacent one of the shifters togenerate a plurality of first control signals.

A display device according to a third aspect of the present inventionincludes a signal controller outputting a gate control signal forcontrolling timing of the gate signals and a plurality of first controlsignals for controlling timing of the data signals, the second controlsignals having timing differences. A gate driver supplies the gatesignals to the gate lines in synchronization with the gate controlsignal. The data lines are grouped into a plurality of blockscorresponding to the first control signals from the signal controllerand a data driver supplies the data signals to the blocks insynchronization with the first control signals.

In the display devices according to the first to the third aspects ofthe present invention, at least one of the timing differences betweenthe first control signals is preferably different from another of thetiming differences.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram of an active matrix display deviceaccording to the first embodiment of the present invention;

FIG. 2 shows gate signals for pixels in a row;

FIG. 3 is a block diagram of a TP signal shifting unit according to thefirst embodiment of the present invention;

FIG. 4 illustrates TP signals generated by a TP signal shifting limitaccording to the first embodiment of the present invention;

FIG. 5 shows data signals applied to data lines according to the firstembodiment of the present invention; and

FIG. 6 is a schematic block diagram of an active matrix display deviceaccording to a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention now will be described in more detail hereinafterwith reference to the accompanying drawings, in which preferredembodiments of the invention are shown. However, thus invention may beembodied in many different forms and should not be construed as limitedto the embodiments set forth herein. Like numerals refer to likeelements throughout.

Then, active matrix display devices according to embodiments of thepresent invention will be described in detail with reference toaccompanying drawings.

Referring to FIGS. 1-5, an active matrix display device according to thefirst embodiment of the present invention is described.

FIG. 1 is a schematic block diagram of an active matrix display deviceaccording to the first embodiment of the present invention and FIG. 2shows gate signals for pixels in a row. FIG. 3 is a block diagram of aTP signal shifting unit according to the first embodiment of the presentinvention and FIG. 4 illustrates TP signals generated by a TP signalshifting unit according to the first embodiment of the presentinvention. FIG. 5 shows data signals applied to data lines according tothe first embodiment of the present invention.

Referring to FIG. 1, a display device according to a first embodiment ofthe present invention includes a display panel 100, a signal controller200, a gate driver 300, a data driver 400, and a TP signal shifting unit500. The display panel 100 includes a plurality of gate lines C1-Cmextending in a transverse direction and a plurality of data lines R1-Rnextending in a longitudinal direction, which are formed thereon. Twoadjacent gate lines and two adjacent data lines define a pixel area, anda transistor 120 for transmitting data signals from a data line to apixel 110 in response to gate signals from a gate line are provided ineach pixel area. The pixel 110 is charged with the data signals todisplay images.

The signal controller 200 receives a vertical synchronization signalVsync for distinguishing frames, a horizontal synchronization signalHsync for distinguishing rows, and a clock signal MCLK from an externalgraphics controller (not shown). The signal controller 200 generatescontrol signals and a TP signal for driving the gate driver 300 and thedata driver 400 based on the received signals to be provided for thegate driver 300 and the data driver 400.

The gate driver 300 sequentially applies the gate signals for turning onthe transistors 120 to the gate lines C1-Cm in response to the controlsignals from the signal controller 200. In case that the gate driver 300applying the gate signals to the gate lines C1-Cm is located at a leftside of the display panel 100, as shown in FIG. 2, the gate signals maybecome delayed and distorted due to load of the gate lines C1-Cm andparasitic capacitances generated between the gate liens C1-Cm and thepixels 110 as they go to the right.

The data driver 400 applies the data signals to the pixels 110 throughthe data lines R1-Rn based on a triggered pulse signal (referred to as“a TP signals” hereinafter) from the signal controller 200. The firstembodiment of the present invention groups the data lines R1-Rn into i(where 2≦i≦n) blocks B1-Bi and supplies TP signals for the respectiveblocks B1-Bi in a staggered manner. Each block may include one data lineor several data lines. The numbers of the data lines R1-Rn in the blocksB1-Bi are equal or different. The time differences in the TP signalsbetween successive blocks are equal or different depending on the delayand the distortion, and they are preferably determined depending on thedelay and the distortion of the gate lines C1-Cm.

The TP signal shifting unit 500 of the display device according to thefirst embodiment of the present invention gives time differences to theTP signal from the signal controller 200 and transmits the asynchronousdifferentiated TAP signals TP_(B1)-TP_(Bi) to the data driver 300. TheTP signal shifting unit 500 is located between the signal controller 200and the data driver 400 or incorporated in the signal controller 200.

An exemplary TP signal shifting unit 500 according to the firstembodiment of the present invention is described in detail withreference to FIGS. 3-5.

As shown in FIG. 3, a TP signal shifting limit 500 includes (i-1)shifters SH₁-SH_(i-1) connected in sequence and receives a TP signalTP_(B1) shown in FIG. 4. The shifter SH₁ shifts TP signal TP_(B1)inputted into the TP signal shifting unit 500 are shifted by apredetermined clock and transmits the shifted TP signal TP_(B2) to anadjacent shifter SH₂. Likewise, the shifters SH₂-SH_(i-1), shifts the TPsignals TP_(B2)-TP_(Bi-1) shifted by the previous shifters SH₁-SH_(i-2)to generate the shifted TP signals TP_(B3)-TP_(Bi).

Then, the TP signal TP_(B1) inputted to the TP signal shifting unit 500and the TP signals TP_(B2)-TP_(Bi) outputted by the shiftersSH₁-SH_(i-1) function as the TP signals for the respective blocks B1-Bi.At this time, the number of clocks shifted by each shifter SH₁-SH_(i-1)is preferably determined in consideration of the delay of the gatesignals for the corresponding block B1-Bi and it is also preferablydetermined enough to secure a blanking period without application of thedata voltages.

The shift of the TP signal to be supplied to the data driver 400differentiates the application time of the data signals to the datalines R1-Rn in the blocks B1-Bi. Since the time difference in theapplication of the data signals between the data lines R1, . . . , Rj, .. . , Rn is substantially equal to the delay of the gate signals asshown in FIG. 5, the charging CH1, . . . , CHj, . . . , CHn of the datasignals in the pixels 110 become substantially uniform. This prevents ashading generated by the delayed gate signals and the data signals for anext row, thereby reducing shading margins to optimize a gate maskingwidth.

The first embodiment of the present invention shifts the TP signal fromthe signals controller 200 by employing the shifters to give timedifference to the data signals for the blocks. However, the signalcontroller 200 can generate separate TP signals for the respectiveblocks without providing independent shifters. Such an embodiment isdescribed in detail hereinafter with reference to FIG. 6.

FIG. 6 is a schematic block diagram of a display device according to asecond embodiment of the present invention.

Referring to FIG. 6, a display device according to a second embodimentof the present invention has nearly the same configuration as the firstembodiment except for the TP signal shifting unit and the signalcontroller 200. A signal controller 200 of the display device accordingto the second embodiment outputs separate TP signals TP_(B1)-TP_(Bi) forrespective blocks B1-Bi including data lines R1-Rn. Accordingly, thereis no TP signal shifting unit 500 of the first embodiment of the presentinvention.

The signal controller 200 separately supplies the IP signals for theblocks B1-Bi to a data driver 400 to make the data driver 400 outputdata signals for pixels connected to the data lines R1-Rn of the blocksB1-Bi. The TP signals TP_(B1)-TP_(Bi) for the respective blocks B1-Bioutputted from the signal controller 200 have the time differencepreferably equal to the delay of gate signals as shown in FIG. 4.Accordingly, since the data signals are applied to the data lines withthe time difference substantially equal to the delay of the gate signalslike the first embodiment of the present invention, the non-uniformcharging of the data signals in the pixels 110 is improved.

The embodiments of the present invention can be applied to all theactive matrix type display devices. For example, when a data driver ofan LCD applies data voltages to be supplied to pixels through data linesin a staggered manner, liquid crystal of each pixel properly responds tothe applied data voltages. Likewise, an E1 display device supplies datavoltages for a sufficient time, an EL element of each pixel is suppliedwith sufficient current to display appropriate grays.

As described above, the embodiments of the present invention solvesnon-uniformity in charging of data voltages resulted from the delay orthe distortion of gate signals applied to gate lines, which is generatedby a load of the gate lines and by parasitic capacitances between thegate lines and pixels and becomes severer at farther places from a gatedriver. In particular, an LCD subject to an inversion driving can reducea shading generated by the delayed gate signals, thereby optimizing agate masking width.

While the present invention has been described in detail with referenceto the embodiments, it is to be understood that the invention is notlimited to the disclosed embodiments, but, on the contrary, is intendedto cover various modifications and equivalent arrangements includedwithin the sprit and scope of the appended claims.

FIG. 6 is a schematic block diagram of a display device according to asecond embodiment of the present invention.

Referring to FIG. 6, a display device according to a second embodimentof the present invention has nearly the same configuration as the firstembodiment except for the TP signal shifting unit and the signalcontroller 200. A signal controller 200 of the display device accordingto the second embodiment outputs separate TP signals TP_(B1)-TP_(Bi) forrespective blocks B1-Bi including data lines R1-Rn. Accordingly, thereis no TP signal shifting unit 500 of the first embodiment of the presentinvention.

The signal controller 200 separately supplies the TP signals for theblocks B1-Bi to a data driver 400 to make the data driver 40D outputdata signals for pixels connected to the data lines R1-Rn of the blocksB1-Bi. The TP signals TP_(B1)-TP_(Bi) for the respective blocks B1-Bioutputted from the signal controller 200 have the time differencepreferably equal to the delay of gate signals as shown in FIG. 4.Accordingly, since the data signals are applied to the data lines withthe time difference substantially equal to the delay of the gate signalslike the first embodiment of the present invention, the non-uniformcharging of the data signals in the pixels 110 is improved.

The embodiments of the present invention can be applied to all theactive matrix type display devices. For example, when a data driver ofan LCD applies data voltages to be supplied to pixels through data linesin a staggered manner, liquid crystal of each pixel properly responds tothe applied data voltages. Likewise, an E1 display device supplies datavoltages for a sufficient time, an EL element of each pixel is suppliedwith sufficient current to display appropriate grays.

As described above, the embodiments of the present invention solvesnon-uniformity in charging of data voltages resulted from the delay orthe distortion of gate signals applied to gate lines, which is generatedby a load of the gate lines and by parasitic capacitances between thegate lines and pixels and becomes severer at farther places from a gatedriver. In particular, an LCD subject to an inversion driving callreduce a shading generated by the delayed gate signals, therebyoptimizing a gate masking width.

While the present invention has been described in detail with referenceto the embodiments, it is to be understood that the invention is notlimited to the disclosed embodiments, but, on the contrary, is intendedto cover various modifications and equivalent arrangements includedwithin the sprit and scope of the appended claims.

FIG. 6 is a schematic block diagram of a display device according to asecond embodiment of the present invention.

Referring to FIG. 6, a display device according to a second embodimentof the present invention has nearly the same configuration as the firstembodiment except for the TP signal shifting unit and the signalcontroller 200. A signal controller 200 of the display device accordingto the second embodiment outputs separate TP signals TP_(B1)-TP_(Bi) forrespective blocks B1-Bi including data lines R1-Rn. Accordingly, thereis no TP signal shifting unit 500 of the first embodiment of the presentinvention.

The signal controller 200 separately supplies the TP signals for theblocks B1-Bi to a data driver 400 to make the data driver 400 outputdata signals for pixels connected to the data lines R1-Rn of the blocksB1-Bi. The TP signals TP_(B1)-TP_(Bi) for the respective blocks B1-Bioutputted from the signal controller 200 have the time differencepreferably equal to the delay of gate signals as shown in FIG. 4.Accordingly, since the data signals are applied to the data lines withthe time difference substantially equal to the delay of the gate signalslike the first embodiment of the present invention, the non-uniformcharging of the data signals in the pixels 110 is improved.

The embodiments of the present invention can be applied to all theactive matrix type display devices. For example, when a data driver ofan LCD applies data voltages to be supplied to pixels through data linesin a staggered manner, liquid crystal of each pixel properly responds tothe applied data voltages. Likewise, an E1 display device supplies datavoltages for a sufficient time, an EL element of each pixel is suppliedwith sufficient current to display appropriate grays.

As described above, the embodiments of the present invention solvesnon-uniformity in charging of data voltages resulted from the delay orthe distortion of gate signals applied to gate lines, which is generatedby a load of the gate lines and by parasitic capacitances between thegate lines and pixels and becomes severer at farther places from a gatedriver. In particular, an LCD subject to an inversion driving can reducea shading generated by the delayed gate signals, thereby optimizing agate masking width.

While the present invention has been described in detail with referenceto the embodiments, it is to be understood that the invention is notlimited to the disclosed embodiments, but, on the contrary, is intendedto cover various modifications and equivalent arrangements includedwithin the sprit and scope of the appended claims.

1. A display device comprising: a display panel including a plurality ofdata lines extending parallel to each other in a column direction, aplurality of gate lines extending parallel to each other in a rowdirection, and a plurality of pixels arranged in a matrix and receivinggate signals and data signals respectively from the gate lines and thedata lines to display images, each pixel including a switching elementtransmitting the data signals in response to the gate signals; a gatedriver supplying the gate signals to the gate lines; and a data driversupplying the data signals to the data lines in synchronization with aplurality of first control signals, wherein the data lines are groupedinto a plurality of blocks, each block including at least one of thedata lines and the first control signals correspond to the respectiveblocks and have different timing.
 2. The display device of claim 1,further comprising a signal controller outputting a timing signal fordriving the display panel and a second control signal; and a controlsignal shifting unit receiving the second control signal and shiftingthe second control signal in sequence to generating the first controlsignals.
 3. The display device of claim 2, wherein the control signalshifting unit comprises a plurality of shifters for sequentiallyshifting the second control signal to be transmitted to adjacentshifters.
 4. The display device of claim 3, wherein the first controlsignals comprises the second control signal and outputs of the shifters.5. The display device of claim 1, further comprising a signal controlleroutputting a timing signal for driving the display panel and a secondcontrol signal.
 6. The display device of claim 1, wherein at least oneof timing differences between the first control signals is differentfrom another of the tiring differences.
 7. A display device comprising:a display panel including a plurality of data lines extending parallelto each other in a column direction, a plurality of gate lines extendingparallel to each other in a row direction, and a plurality of pixelsarranged in a matrix and receiving gate signals and data signalsrespectively from the gate lilies and the data lines to display images,each pixel including a switching element transmitting the data signalsin response to the gate signals; a signal controller outputting firstand second control signals for controlling timings of the gate signalsand the data signals, respectively; a gate driver supplying the gatesignals to the gate lines in synchronization with the first controlsignal from the signal controller; a control signal shifting unitshifting the second control signal in sequence to generate a pluralityof third control signals having timing differences; and a data driversupplying the data signals to a plurality of blocks of the data lines insynchronization with the third control signals from the control signalshifting unit, each block including at least one of the data lines andcorresponding to one of the third control signals.
 8. The display deviceof claim 7, wherein the control signal shifting unit comprises aplurality of shifters generating the third control signals bysequentially shifting the second control signal to be transmitted toadjacent one of the shifters.
 9. The display device of claim 7, whereinat least one of the timing differences between the third control signalsis different from another of the timing differences.
 10. A displaydevice comprising: a display panel including a plurality of data linesextending parallel to each other in a column direction, a plurality ofgate lines extending parallel to each other in a row direction, and aplurality of pixels arranged in a matrix and receiving gate signals anddata signals respectively from the gate lines and the data lines todisplay images, each pixel including a switching element transmittingthe data signals in response to the gate signals; a signal controlleroutputting a first control signal for controlling timing of the gatesignals and a plurality of second control signals for controlling timingof the data signals, the second control signals having timingdifferences; a gate driver supplying the gate signals to the gate linesin synchronization with the first control signal; and a data driversupplying the data signals to a plurality of blocks of the data lines insynchronization with the second control signals from the signalcontroller, each block including at least one of the data lines andcorresponding to one of the third control signals.
 11. The displaydevice of claim 10, wherein at least one of the timing differencesbetween the second control signals is different from another of thetiming differences.